L. M. d’Oliveira, V. Kilchytska, D. Flandre, and M. de Souza. Self-Cascode Current-Voltage Curve-Construction Algorithm from Single MOSFET Measurements for Analog Figures-of-Merit Extraction. Journal of Integrated Circuits and Systems, 14(1):1–6, April 2019.

R. Assalti, L. M. d’Oliveira, M. A. Pavanello, D. Flandre, and M. de Souza. Experimental and simulation analysis of electrical characteristics of commonsource current mirrors implemented with asymmetric self-cascode silicon-oninsulator n-channel metal–oxide–semiconductor field-effect transistors. IET Circuits, Devices Systems, 10(4):349–355, 2016.

L. M. d’Oliveira, V. Kilchytska, D. Flandre, and M. de Souza. Harmonic distortion on symmetric and asymmetric self-cascodes of UTBB FD SOI planar MOSFETs. In 34th Symposium on Microelectronics Technology and Devices (SBMicro), São Paulo, August 2019. IEEE.

L. M. d’Oliveira, V. Kilchytska, D. Flandre, N. Planes, and M. de Souza. Subthreshold operation of self-cascode structure using UTBB FD SOI planar MOSFETs. In IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, October 2019.

L. M. d’Oliveira, M. de Souza, V. Kilchytska, and D. Flandre. Asymmetric Self-Cascode Current-Voltage Constructing Algorithm for Analog Figures-of-Merit Extraction. In 2018 33rd Symposium on Microelectronics Technology and Devices (SBMicro), pages 1–4, August 2018.

L. M. d’Oliveira, M. de Souza, V. Kilchytska, and D. Flandre. Design benefits of self-cascode configuration for analog applications in 28 FDSOI. In 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), pages 1–3, Granada, March 2018. IEEE.

L. M. d’Oliveira and M. de Souza. Threshold voltage of UTBB self-cascode structures with different ground planes. In XI Workshop on Semiconductors and Micro and Nano-Technology (Seminatec), Campinas, 2016.

L. M. d’Oliveira, R. T. Doria, and M. de Souza. Effects of high temperature on the harmonic distortion of the asymmetric self-cascode of SOI nMOSFETs. In X Workshop on Semiconductors and Micro and Nano Technology (Seminatec), São Bernardo do Campo, 2015.

L. M. d’Oliveira, R. T. Doria, M. A. Pavanello, D. Flandre, and M. de Souza. Effect of channel doping concentration on the harmonic distortion of asymmetric n- and p-type self-cascode MOSFETs. In 2015 30th Symposium on Microelectronics Technology and Devices (SBMicro), September 2015.

L. M. d’Oliveira, R. T. Doria, M. A. Pavanello, M. de Souza, and D. Flandre. Analysis of harmonic distortion of asymmetric self-cascode association of SOI nMOSFETs operating in saturation. In 2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS), pages 1–6, April 2014.

R. Assalti, L. M. d’Oliveira, M. A. Pavanello, and M. de Souza. Performance of common-source current mirrors with asymmetric self-cascode SOI nMOSFETs. In EuroSOI 2014 - Tenth Workshop of the Thematic Network on Silicon on Insulator, Technology, Devices and Circuits, Tarragona, 2014.

L. M. d’Oliveira, D. Flandre, M. A. Pavanello, and M. de Souza. Effect of high temperature on analog parameters of asymmetric self-cascode SOI nMOSFETs. In 2014 29th Symposium on Microelectronics Technology and Devices (SBMicro), Aracajú, September 2014.

L. M. d’Oliveira, R. T. Doria, M. A. Pavanello, V. Kilchytska, D. Flandre, and M. de Souza. Asymmetric self-cascode FD SOI nMOSFETs harmonic distortion at cryogenic temperatures. In 2014 11th International Workshop on Low Temperature Electronics (WOLTE), pages 57–60, Grenoble, July 2014. IEEE.

L. M. d’Oliveira, R. T. Doria, and M. de Souza. Comparison of harmonic distortion of SOI nMOS symmetric and asymmetric self-cascode associations. In IX Workshop on Semiconductors and Micro and Nano Technology (Seminatec), São Paulo, 2014.

L. M. d’Oliveira and M. de Souza. Effect of temperature reduction on analog parameters of single gate SOI transistors. In Chip in Curitiba - 13th Microelectronics Students Forum, Curitiba, August 2013.

L. M. d’Oliveira and M. de Souza. Efeito da redução da temperatura em parâmetros analógicos de transistores SOI de porta Única. In Simpósio de Pesquisa do Grande ABC (SPGABC), São Bernardo do Campo, 2013.

L. M. d’Oliveira and M. de Souza. Simulação de transistores mos convencionais e soi de porta Única e dupla. In I Simpósio de Iniciação Científica, Didática e de Ações Sociais de Extensão da FEI (SICFEI), São Bernardo do Campo, 2011.

L. M. d’Oliveira and M. de Souza. Efeito da redução do comprimento de canal em transistores SOI de porta Única e dupla. In 13o Simpósio de Iniciação Científica e Tecnológica, volume BT/31, pages 67–68, São Paulo, 2011.